Semiconductor dies are typically manufactured on a semiconductor wafer. A wafer may have many (e.g., hundreds) dies. Testing of the dies is typically performed to allow defective dies to be identified. To perform testing of the dies, the dies are typically placed into a tester. Electrical connection to the dies is typically provided by a probe card assembly. The probe card assembly includes probes, which can be brought into contact with bond pads and/or other terminals on the semiconductor dies to form temporary electrical connections between the tester and the dies. The tester can apply power and test data inputs to the dies, and monitor data outputs from the dies to determine if the dies are operating correctly.
Testing large numbers of dies in parallel is desirable, since this can reduce the test time and increase tester throughput. As wafers have become larger, the number of dies on a single wafer can exceed the available resources of a tester. Various techniques have been developed for sharing data inputs and outputs from multiple dies on a single tester channel allowing for some increase in parallel test capacity.
Powering large numbers of dies can prove to be difficult, however. In some situations, the amount of power the tester can provide may be insufficient to power a desired number of dies. Some die designs use lower power voltages, which can result in decreased power efficiency of the tester when linear regulators are used in the tester. Some die designs use an increased number of different power voltages. Some die designs require the power voltage to change when operating in different modes. These issues present obstacles to powering and testing large numbers of dies in parallel.